////////////////////////////////////////////////////////////////////////////// 
//
//  jtag_reg.v
//
//  通用寄存器，可通过JTAG TAP控制器读取或写入。
//  注意，这没有单独的移位和更新阶段，所以寄存器的使用者必须在更新时限定输出
//
//  Original Author: 
//  Current Owner:   
//
////////////////////////////////////////////////////////////////////////////// 
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
////////////////////////////////////////////////////////////////////////////// 
//
//    Perforce Information
//    $Author: 
//    $File: /rtl/jtag_reg.v $
//    $DateTime: 
//    $Revision: 
//
////////////////////////////////////////////////////////////////////////////// 

`timescale 1ns/10fs
module np_jtag_reg #(parameter WIDTH=2,
                  parameter [WIDTH-1:0] RST_VAL = 0) (
output reg [WIDTH-1:0]  q,
output wire             serial_out,
input  wire             rst,
input  wire             clk,
input  wire             capture,
input  wire             shift,
input  wire             select,
input  wire [WIDTH-1:0] capture_val,
input  wire             serial_in
);

// 寄存器在计时但不移位时捕获并行capture_val数据。
// 当移位时，最低有效位(LSB)移至串行输出（serial_out），
// 最高有效位（MSB）通过串行输入（serial_in）置位。
//
assign serial_out = q[0];

// 需要对单比特情况进行特殊处理，因为单比特的移位操作不同
//
generate
  if (WIDTH == 1) begin: single_bit_gen
    always @(posedge clk or posedge rst)
      if (rst)
        q <= RST_VAL;
      else if (select) begin
        if (shift)
          q <= serial_in;
        else if (capture)
          q <= capture_val;
      end
  end 
  else begin: multi_bit_gen
    always @(posedge clk or posedge rst)
      if (rst)
	q <= RST_VAL;
      else if (select) begin
	if (shift)
        q <= {serial_in, q[WIDTH-1:1]};
	else if (capture)
          q <= capture_val;
      end
  end
endgenerate

endmodule
